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A novel SRAM-based FPGA architecture for defect and fault tolerance of configurable logic blocks

Abstract : In this paper we propose a novel SRAM-based FPGA architecture suited for mapping designs when defect and fault tolerance are needed. The proposed fault tolerant (FT) method employ triple modular redundancy (TMR) combined with master-slave technique (MST). Specifically, the FT-based MST technique aims to build up the SRAM-based FPGA by master-slave units (MSU). Each MSU consists of two kinds of configurable logic blocks (CLB): CLB-master (CLB-M) and CLB-slave (CLB-S). With this new architecture both, single and double faults can be tolerated when they occur in the MSU unit by using partial reconfiguration. Our proposed approach provides also accurate location of the faulty CLB-M. In this paper, we prove that the reliability of the proposed method is greater than that proposed by other previous work employing similar overhead.
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Conference papers
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https://hal-utt.archives-ouvertes.fr/hal-02563086
Contributor : Jean-Baptiste Vu Van <>
Submitted on : Tuesday, May 5, 2020 - 9:45:10 AM
Last modification on : Wednesday, May 6, 2020 - 1:41:46 AM

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Farid Lahrach, Abderrazek Abdaoui, Abderrahim Doumar, Eric Chatelet. A novel SRAM-based FPGA architecture for defect and fault tolerance of configurable logic blocks. 2010 IEEE 13th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Apr 2010, Vienna, Austria. pp.305-308, ⟨10.1109/DDECS.2010.5491763⟩. ⟨hal-02563086⟩

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