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Fault tolerance of SRAM-based FPGA via configuration frames

Abstract : Fault tolerance is an important system metric to increase chip reliability. The conventional technique for improving system reliability is through component replication, which usually comes at significant cost: increased design time, testing, power consumption, volume and weight. In this contribution, we propose a technique based on partial dynamic reconfiguration (PDR) to tolerate faults in configurable logic blocks (CLBs) and routing resources (RRs). The fault tolerance is achieved through SRAM cells of configuration frames. Our method do not require preallocated spare CLBs or RRs. The reliability of frames is analyzed and improved.
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https://hal-utt.archives-ouvertes.fr/hal-02317777
Contributor : Jean-Baptiste Vu Van <>
Submitted on : Wednesday, October 16, 2019 - 12:29:04 PM
Last modification on : Thursday, October 17, 2019 - 1:27:39 AM

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Farid Lahrach, Abderrahim Doumar, Eric Chatelet. Fault tolerance of SRAM-based FPGA via configuration frames. Systems (DDECS), Apr 2011, Cottbus, Germany. pp.139-142, ⟨10.1109/DDECS.2011.5783066⟩. ⟨hal-02317777⟩

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