Master-Slave TMR Inspired Technique for Fault Tolerance of SRAM-Based FPGA

Farid Lahrach (1) , Abderrahim Doumar (1) , Eric Chatelet (1) , Abderrazek Abdaoui (1)

1 LM2S - Laboratoire Modélisation et Sûreté des Systèmes

In order to increase reliability and availability of Static-RAM based field programmable gate arrays (SRAM-based FPGAs), several methods of tolerating defects and permanent faults have been developed and applied. These methods are not well adapted for handling high fault rates for SRAM based FPGAs. In this paper, both single and double faults affecting configurable logic blocks (CLBs) are addressed. We have developed a new fault-tolerance technique that capitalizes on the partial reconfiguration capabilities of SRAM-based FPGA. The proposed fault-tolerance method is based on triple modular redundancy (TMR) combined with master-slave technique, and exploiting partial reconfiguration to tolerate permanent faults. Simulation results on reliability improvement corroborate the efficiency of the proposed method and prove that it compares favorably to previous methods.

Domains: Modeling and Simulation

Farid Lahrach, Abderrahim Doumar, Eric Chatelet, Abderrazek Abdaoui. Master-Slave TMR Inspired Technique for Fault Tolerance of SRAM-Based FPGA. 2010 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Jul 2010, Lixouri, Greece. pp.58-62, ⟨10.1109/ISVLSI.2010.38⟩. ⟨hal-02269699⟩